(1) Field of the Invention
The present invention relates to the manufacturing of semiconductor memories, and in particular, directed to a split-gate flash memory having a shallow trench isolation with a xe2x80x9cnon-smilingxe2x80x9d structure and to a method of forming the same.
(2) Description of the Related Art
The conventional split-gate flash memory cell of FIG. 1a, as practiced in the present manufacturing line, is found to exhibit relatively small capacitive coupling and low data retention capability. This is because, the relatively thick gate oxide (20) separating the floating gate (30) from the substrate (10) contributes to the reduced coupling between the floating gate (30) and the source (15) due to the so-called xe2x80x9csmiling effectxe2x80x9d. Reference numerals (13) refer to the drain regions in the cell. Smiling effect occurs at the edge of the floating gate which can be better seen in the enlarged view in FIG. 1b. As is known in the art, floating gate (30) is separated from substrate (10) by the intervening gate oxide layer (20) and from the control gate (50) by the intervening intergate oxide (40) layer as shown in FIG. 1a. Floating gate, including the overlying polyoxide (35) xe2x80x9ccapxe2x80x9d, and the xe2x80x9csmilingxe2x80x9d structure are shown in FIG. 1b. 
xe2x80x9cSmilingxe2x80x9d effect refers to the thickening of the edges (25), or xe2x80x9clipsxe2x80x9d of the gate oxide underlying the polysilicon floating gate of a memory cell causedxe2x80x94as will be apparent to those skilled in the artxe2x80x94by the diffusion of oxygen (60) during the forming of the polyoxide (35) over the gate as shown in FIG. 1b. That is, during oxidation, oxygen (60) diffuses into the gate (30) as well as into gate oxide (20) through its edges (25) and grows the edges as shown in FIG. 1b. Hence the thickness (b) at edge (25) becomes larger than its original thickness (a), thereby resulting in a structure having a xe2x80x9csmilingxe2x80x9d effect.
The same xe2x80x9csmilingxe2x80x9d effect is found in the prior art of shallow trench isolation (STI) as shown in FIG. 1c as well. Trench (90) depicted in FIG. 1c is lined with an oxide layer (80) prior to being filled with isolation oxide (85). Because oxygen (60) diffuses also readily in oxide, a xe2x80x9csmilingxe2x80x9d effect develops at edges (70) forming large xe2x80x9clipsxe2x80x9d as shown in FIG. 1c. The thickness and shape of the edge xe2x80x9clipsxe2x80x9d play an important role in the data retention and the coupling between the gate and the source of a memory cell as will be described more fully below. It is disclosed in this invention a xe2x80x9cnon-smilingxe2x80x9d memory cell structure with a self-aligned STI and a method to form the same. It is further disclosed that the method used provides smaller devices which in turn increase the scale of integration of semiconductor chips.
The importance of data retention capacity and the coupling between the gate and the source of a memory cell has been well recognized since the advent of the one-transistor cell memory cell with one capacitor. Over the years, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improve its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Generally, flash EEPROM cells having both functions of electrical programming and erasing may be classified into two categories, namely, a stack-gate structure and a split-gate structure. A conventional stack-gate type cell is shown in FIG. 2a where, as is well known, tunnel oxide film (120), a floating gate (130), an interpoly insulating film (140) and a control gate (150) are sequentially stacked on a silicon substrate (100) between a drain region (113) and a source region (115) separated by channel region (117). Substrate (100) and channel region (117) are of a first conductivity type, and the first (113) and second (115) doped regions are of a second conductivity type that is opposite the first conductivity type.
One of the problems that is encountered in flash memories is the xe2x80x9cover-erasurexe2x80x9d of the memory cell contents during erasure operations. As seen in FIG. 2a, the stacked-gate transistor is capable of injecting electrons from drain (113), based on a phenomenon known as the Fowler-Nordheim Tunneling Effect, through tunneling oxide layer (120) into floating gate (130). The threshold voltage of a stacked-gate transistor can be raised by means of such electron injection, and the device is then assumes a first state that reflect the content of the memory cell. On the other hand, during erasure of the memory cell, electrons are expelled from the source (115) through tunneling oxide layer (120) and out of floating gate (130) of the transistor. As a result of this electron removal, the threshold voltage is lowered and thus the device then assumes a second memory state.
During the process of memory content erasure, however, to ensure complete removal of the electrons previously injected, the erasure operation is normally sustained for a slightly prolonged time period. There are occasions when such a prolonged erasure operation results in the removal of excess electrons, i.e., more electrons than were previously injected. This results in the formation of electron holes in the floating gate of the device. In severe cases, the stacked-gate transistor becomes a depletion transistor, which conducts even in the absence of the application of a control voltage at the control gate, (150). This phenomenon is known in the art as memory over-erasure.
To overcome the described memory over-erasure problem of stacked-gate type EEPROM devices, a split-gate EEPROM device is used as shown in FIG. 2b. This memory device comprises floating-gate transistor which similarly includes control gate (150xe2x80x2), floating gate (130xe2x80x2) as in the case of the stacked-gate transistor of FIG. 2a. However, floating gate (130xe2x80x2) here covers only a portion of the channel region, (117xe2x80x2), and the rest of the channel region, (119xe2x80x2), is directly controlled by control gate (150xe2x80x2). This split-gate-based memory cell is equivalent to a series connected floating-gate transistor (117xe2x80x2) and an enhanced isolation transistor (119xe2x80x2), as is schematically represented in FIG. 2b. The principal advantage of such configuration is that isolation transistor (119xe2x80x2) is free from influence of the state of floating gate (117xe2x80x2) and remains in its off-state, even if floating-gate transistor (117xe2x80x2) is subjected to the phenomenon of over-erasure and therefore, is in a conductive state. The memory cell can thus maintain its correct state irrespective of the over-erasure problem.
However, the greatest drawback of such split-gate design is the fact that a reduced number of program/erase cycles are allowed. This reduction is due to the fact that floating gate (130xe2x80x2) of this split-gate memory cell configuration is only provided near the drain region (113xe2x80x2), which results in different mechanisms occurring for the programming and erasing operations of the device. That is, electron passage must be via a sequence of drain (113xe2x80x2) and through tunneling oxide layer (120xe2x80x2), and the resulting reduction of allowable program/erase cycles renders the device suitable only for those applications requiring a relatively few number of program/erase cycles during the entire life span of the device.
To program the transistor shown in FIG. 2b, charge is transferred from substrate (100) through gate oxide (120xe2x80x2) and is stored on floating gate (130xe2x80x2) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed xe2x80x9conxe2x80x9d of xe2x80x9coff.xe2x80x9d xe2x80x9cReadingxe2x80x9d of the cell""s state is accomplished by applying appropriate voltages to the cell source (115xe2x80x2) and drain (113xe2x80x2), and to control gate. (150xe2x80x2), and then sensing the amount of charge on floating gate (130xe2x80x2). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling mentioned above. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of (F-N) tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Usually a thickness of between about 80 to 120 Angstroms is required to facilitate F-N tunneling.
The thicknesses of the various portions of the oxide layers on the split-gate side (between the control gate and the source) and the stacked-side (between the floating gate and the drain) of the memory cell of FIG. 2b play an important role in determining such parameters as current consumption, coupling ratio and the memory erase-write speed. In prior art, various methods have been developed to address these parameters. For example, in U.S. Pat. No. 5,716,865 Ahn uses a thick insulation film between the tunneling region and the channel region in an EEPROM split-gate flash memory cell in order to prevent the degradation of the tunnel oxide film due to the band-to-band tunneling and the secondary hot carriers which are generated by a high electric field formed at the overlap regions between the junction region and the gate electrode when programming and erasure operations are performed with high voltage.
Wang, in U.S. Pat. No. 5,597,751 shows a method of preventing shorting between a floating gate and a source/drain region of a substrate by depositing a thick spacer oxide layer on top of the floating gate and the source/drain region to a sufficient thickness such that electrical insulation is provided therebetween.
Fahey, et al., on the other hand, disclose a method of forming shallow trench isolation by using a nitride liner with a thickness less than 5 nanometers (nm) in order to prevent the formation of unacceptable voids in the trench. The present invention discloses a different method of fabricating a split-gate memory device with a self-aligned isolation of a non-smiling structure to affect better performance.
It is therefore an object of this invention to provide a method of forming a split-gate flash memory having a shallow trench isolation with a xe2x80x9cnon-smilingxe2x80x9d structure.
It is an overall object of this invention to provide a split-gate flash memory cell having a shallow trench isolation with a xe2x80x9cnon-smilingxe2x80x9d structure, reduced size, and increased coupling between the floating gate and the source.
These objects are accomplished by providing a semiconductor substrate; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming a pad oxide layer over said first polysilicon layer; forming a first nitride layer over said pad oxide layer; forming and patterning a first photoresist layer over said first nitride layer to define active regions in said substrate; forming a trench in said substrate by etching through patterns in said first photoresist layer; removing said first photoresist layer; forming a first conformal lining on the inside walls of said trench; forming a second conformal lining over said first conformal lining a second conformal lining over said first conformal lining on the inside walls of said trench; depositing isolation oxide inside said trench to from shallow trench isolation (STI); performing chemical-mechanical polishing of said substrate; removing said first nitride layer; removing said pad oxide layer; forming second nitride layer over said substrate; forming and patterning a second photoresist layer over said second nitride layer to define floating gate; etching through patterns in said second photoresist layer to form openings in said second nitride layer exposing portions of said first polysilicon layer; removing said second photoresist layer; performing thermal oxidation of exposed said portions of said first polysilicon layer through said openings in said second nitride layer to form polyoxide hard mask; removing said second nitride layer; etching said first polysilicon layer using said polyoxide as a hard mask; forming intergate oxide layer; forming a second polysilicon layer over said intergate oxide layer; forming and patterning a third photoresist layer over said second intergate oxide layer to define control gate; and etching through said patterning in third photoresist layer to complete the forming of said split-gate flash memory.
These objects are further accomplished by providing a split-gate flash memory cell having appropriate gate oxide thicknesses between the substrate and the floating gate and between the floating gate and the control gate along with an extra thin nitride layer lining the inside walls of the shallow trench isolation (STI) in order to overcome the problems of low data retention capacity and reduced capacitive coupling of a conventional cell.